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1/17 may 2002 M68AR256ML 4 mbit (256k x16) 1.8v asynchronous sram features summary n supply voltage: 1.65 to 1.95v n 256k x 16 bits sram with output enable n equal cycle and access time: 55ns n single byte read/write n low standby current n low v cc data retention: 1.0v n tri-state common i/o n automatic power down figure 1. packages bga tfbga48 (zb) 7 x 8 mm
M68AR256ML 2/17 table of contents summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 figure 3. tfbga connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 4. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 2. absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 5. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 6. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 table 4. capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 5. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 6. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 7. address controlled, read mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 8. chip enable or output enable controlled, read mode ac waveforms . . . . . . . . . . . . . . 9 figure 9. chip enable or ub/lb controlled, standby mode ac waveforms . . . . . . . . . . . . . . . . . . 9 table 7. read and standby mode ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 10. write enable controlled, write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 11. chip enable controlled, write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 8. write mode ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 13. low vcc data retention ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 9. low v cc data retention characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 tfbga48 7x8mm - 6x8 ball array, 0.75 mm pitch, bottom view package outline. . . . . . . . . . . . . 15 tfbga48 7x8mm - 6x8 ball array, 0.75 mm pitch, package mechanical data. . . . . . . . . . . . . . . . 15 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 11. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 12. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3/17 M68AR256ML summary description the M68AR256ML is a 4 mbit (4,194,304 bit) cmos sram, organized as 262,144 words by 16 bits. the device features fully static operation re- quiring no external clocks or timing strobes, with equal address access and cycle times. it requires a single 1.8v ( 150mv) supply. this device has an automatic power-down feature, reducing the pow- er consumption by over 99% when deselected. the M68AR256ML is available in tfbga48 (0.75 mm pitch) package. figure 2. logic diagram table 1. signal names ai04890 18 a0-a17 w dq0-dq15 v cc M68AR256ML g 16 e ub lb v ss a0-a17 address inputs dq0-dq15 data input/output e chip enable g output enable w write enable ub upper byte enable input lb lower byte enable input v cc supply voltage v ss ground nc not connected internally du dont use as internally connected
M68AR256ML 4/17 figure 3. tfbga connections (top view through package) ai04882 a 6 5 4 3 2 1 e b f a1 a0 g lb a17 dq7 w a12 du a11 a8 nc dq0 a3 a6 a5 a4 e a10 a9 a13 a7 a2 nc c dq4 d dq5 a14 a15 g h dq11 nc ub dq10 dq12 dq13 v ss dq15 dq8 dq9 dq14 dq3 dq2 dq1 v cc v cc nc v ss dq6 a16
5/17 M68AR256ML figure 4. block diagram maximum rating stressing the device above the rating listed in the absolute maximum ratings" table may cause per- manent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not im- plied. exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality docu- ments. table 2. absolute maximum ratings note: 1. one output at a time, not to exceed 1 second duration. 2. up to a maximum operating v cc of 1.95v only. ai04833 row decoder a7 a17 (8) dq0 dq15 (8) column decoder i/o circuits a0 a6 e w g memory array v cc v ss lb lb ub (8) (8) ub lb ub lb symbol parameter value unit i o (1) output current 20 ma t a ambient operating temperature C55 to 125 c t stg storage temperature C65 to 150 c v cc supply voltage C0.5 to 2.5 v v io (2) input or output voltage C0.5 to v cc + 0.5 v p d power dissipation 1 w
M68AR256ML 6/17 dc and ac parameters this section summarizes the operating and mea- surement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measure- ment conditions listed in the relevant tables. de- signers should check that the operating conditions in their projects match the measurement condi- tions when using the quoted parameters. table 3. operating and ac measurement conditions figure 5. ac measurement i/o waveform figure 6. ac measurement load circuit parameter M68AR256ML v cc supply voltage 1.65 to 1.95v ambient operating temperature range 1 0 to 70c range 6 C40 to 85c load capacitance (c l ) 30pf output circuit protection resistance (r 1 ) 15.3k w load resistance (r 2 ) 11. 3k w input rise and fall times 1ns/v input pulse voltages 0 to v cc input and output timing ref. voltages v cc /2 output transition timing ref. voltages v rl = 0.3v cc ; v rh = 0.7v cc ai04831 v cc i/o timing reference voltage 0v v cc /2 v cc output timing reference voltage 0v 0.7v cc 0.3v cc ai03853 v cc out c l includes probe and 1ttl capacitance device under test c l r 1 r 2
7/17 M68AR256ML table 4. capacitance note: 1. sampled only, not 100% tested. 2. at t a = 25c, f = 1 mhz, v cc = 1.8v. table 5. dc characteristics note: 1. average ac current, cycling at t avav minimum. 2. e = v il , lb or/and ub = v il , v in = v il or v ih . 3. e 0.2v, lb or/and ub 0.2v, v in 0.2v or v in 3 v cc C0.2v. 4. output disabled. symbol parameter (1,2) test condition min max unit c in input capacitance on all pins (except dq) v in = 0v 6pf c out output capacitance v out = 0v 8pf symbol parameter test condition min typ max unit i cc1 (1,2) operating supply current v cc = 1.95v, f = 1/t avav , i out = 0ma 26ma i cc2 (3) operating supply current v cc = 1.95v, f = 1mhz, i out = 0ma 12ma i li input leakage current 0v v in v cc C1 1 a i lo (4) output leakage current 0v v out v cc (3) C1 1 a i sb standby supply current cmos v cc = 1.95v, e 3 v cc C0.2v or lb =ub 3 v cc C0.2v, f = 0 0.5 8 a v ih input high voltage 1.4 v cc + 0.4 v v il input low voltage C0.5 0.4 v v oh output high voltage i oh = C100a 1.5 v v ol output low voltage i ol = 100a 0.2 v
M68AR256ML 8/17 operation the M68AR256ML has a chip enable power down feature which invokes an automatic standby mode whenever either chip enable is de-asserted (e = high) or lb and ub are de-asserted (lb and ub = high). an output enable (g ) signal provides a high speed tri-state control, allowing fast read/ write cycles to be achieved with the common i/o data bus. operational modes are determined by device control inputs w , e , lb and ub as summa- rized in the operating modes table (see table 6). table 6. operating modes x = v ih or v il . read mode the M68AR256ML is in the read mode whenever write enable (w ) is high with output enable (g ) low, and chip enables (e ) is asserted. this pro- vides access to data from eight or sixteen, de- pending on the status of the signal ub and lb , of the 4,194,304 locations in the static memory array, specified by the 18 address inputs. valid data will be available at the eight or sixteen output pins within t avqv after the last stable address, provid- ing g is low and e is low. if chip enable or output enable access times are not met, data access will be measured from the limiting parameter (t elqv , t glqv or t blqv ) rather than the address. data out may be indeterminate at t elqx , t blqx and t glqx , but data lines will always be valid at t avqv . figure 7. address controlled, read mode ac waveforms note: e = low, g = low, w = high, ub = low and/or lb = low. operation e w g lb ub dq0-dq7 dq8-dq15 power deselected v ih x x x x hi-z hi-z standby (i sb ) deselected x x x v ih v ih hi-z hi-z standby (i sb ) lower byte read v il v ih v il v il v ih data output hi-z active (i cc ) lower byte write v il v il x v il v ih data input hi-z active (i cc ) output disabled v il v ih v ih x x hi-z hi-z active (i cc ) upper byte read v il v ih v il v ih v il hi-z data output active (i cc ) upper byte write v il v il x v ih v il hi-z data input active (i cc ) word read v il v ih v il v il v il data output data output active (i cc ) word write v il v il x v il v il data input data input active (i cc ) ai03956 tavav tavqv taxqx a0-a17 dq0-dq7 and/or dq8-dq15 valid data valid
9/17 M68AR256ML figure 8. chip enable or output enable controlled, read mode ac waveforms note: write enable (w ) = high. figure 9. chip enable or ub /lb controlled, standby mode ac waveforms ai03957 tavav tavqv taxqx telqv telqx tehqz tglqv tglqx tghqz valid a0-a17 e g dq0-dq15 valid tblqv tblqx tbhqz ub, lb ai03856 tpd i cc tpu i sb 50% e, ub, lb
M68AR256ML 10/17 table 7. read and standby mode ac characteristics note: 1. test conditions assume transition timing reference level = 0.3v cc or 0.7v cc . 2. at any given temperature and voltage condition, t ghqz is less than t glqx , t bhqz is less than t blqx and t ehqz is less than t elqx for any given device. 3. these parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to o utput voltage levels. 4. tested initially and after any design or process changes that may affect these parameters. symbol parameter M68AR256ML unit 55 70 t avav read cycle time min 55 70 ns t av qv address valid to output valid max 55 70 ns t axqx (1) data hold from address change min 5 5 ns t bhqz (2,3) upper/lower byte enable high to output hi-z max 20 25 ns t blqv upper/lower byte enable low to output valid max 55 70 ns t blqx (1) upper/lower byte enable low to output transition min 5 5 ns t ehqz (2,3) chip enable high to output hi-z max 20 25 ns t elqv chip enable low to output valid max 55 70 ns t elqx (1) chip enable low to output transition min 5 5 ns t ghqz (2,3) output enable high to output hi-z max 20 25 ns t glqv output enable low to output valid max 25 35 ns t glqx (2) output enable low to output transition min 5 5 ns t pd (4) chip enable or ub /lb high to power down max 0 0 ns t pu (4) chip enable or ub /lb low to power up min 55 70 ns
11/17 M68AR256ML write mode the M68AR256ML is in the write mode whenever the w and e are low. either the chip enable input (e ) or the write enable input (w ) must be de- asserted during address transitions for subsequent write cycles. when e (w ) is low, and ub or lb is low, write cycle begins on the w (e )'s falling edge. when e and w are low, and ub = lb = high, write cycle begins on the first falling edge of ub or lb . therefore, address setup time is referenced to write enable, chip enable or ub /lb as t avwl , t avel and t avbl respectively, and is determined by the latter occurring edge. the write cycle can be terminated by the earlier rising edge of e , w or ub /lb . if the output is enabled (e = low, g = low, lb or ub = low), then w will return the outputs to high impedance within t wlqz of its falling edge. care must be taken to avoid bus contention in this type of operation. data input must be valid for t dvwh before the rising edge of write enable, or for t dveh before the rising edge of e , or for t dvbh before the rising edge of ub /lb whichever occurs first, and remain valid for t whdx , t ehdx and t bhdx respec- tively. figure 10. write enable controlled, write ac waveforms ai03958 tavav twhax tdvwh data input a0-a17 e w dq0-dq15 valid tavwh twlwh tavwl twlqz twhdx twhqx tblwh ub, lb telwh data (1) data (1)
M68AR256ML 12/17 figure 11. chip enable controlled, write ac waveforms figure 12. ub /lb controlled, write ac waveforms note: 1. during this period dq0-dq15 are in output state and input signals should not be applied. ai03959 tavav tehax tdveh a0-a17 e w dq0-dq15 valid taveh tavel teleh tehdx data input tbleh ub, lb twleh ai03987 tavav tbhax tdvbh data input a0-a17 e w dq0-dq15 valid tavbh tbhdx tblbh ub, lb data (1) tavbl telbh twlbh
13/17 M68AR256ML table 8. write mode ac characteristics note: 1. at any given temperature and voltage condition, t wlqz is less than t whqx for any given device. 2. these parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to o utput voltage levels. symbol parameter M68AR256ML unit 55 70 t avav write cycle time min 55 70 ns t av bh address valid to lb , ub high min 45 60 ns t avbl addess valid to lb , ub low min 0 0 ns t av eh address valid to chip enable high min 45 60 ns t avel address valid to chip enable low min 0 0 ns t av wh address valid to write enable high min 45 60 ns t avwl address valid to write enable low min 0 0 ns t bhax lb , ub high to address transition min 0 0 ns t bhdx lb , ub high to input transition min 0 0 ns t blbh lb , ub low to lb , ub high min 45 60 ns t bleh lb , ub low to chip enable high min 45 60 ns t blwh lb , ub low to write enable high min 45 60 ns t dvbh input valid to lb , ub high min 25 30 ns t dveh input valid to chip enable high min 25 30 ns t dvwh input valid to write enable high min 25 30 ns t ehax chip enable high to address transition min 0 0 ns t ehdx chip enable high to input transition min 0 0 ns t elbh chip enable low to lb , ub high min 45 60 ns t eleh chip enable low to chip enable high min 45 60 ns t elwh chip enable low to write enable high min 45 60 ns t whax write enable high to address transition min 0 0 ns t whdx write enable high to input transition min 0 0 ns t whqx (1) write enable high to output transition min 5 5 ns t wlbh write enable low to lb , ub high min 45 60 ns t wleh write enable low to chip enable high min 45 60 ns t wlqz (1,2) write enable low to output hi-z max 20 20 ns t wlwh write enable low to write enable high min 45 60 ns
M68AR256ML 14/17 figure 13. low v cc data retention ac waveforms table 9. low v cc data retention characteristics note: 1. all other inputs at v ih 3 v cc C0.2v or v il 0.2v. 2. tested initially and after any design or process changes that may affect these parameters. t avav is read cycle time. 3. no input may exceed v cc +0.2v. symbol parameter test condition min typ max unit i ccdr (1) supply current (data retention) v cc = 1.0v, e 3 v cc C0.2v or ub = lb 3 v cc C0.2v, f = 0 (3) 0.5 3 a t cdr (1,2) chip deselected to data retention time 0 ns t r (2) operation recovery time t avav ns v dr (1) supply voltage (data retention) e 3 v cc C0.2v or ub = lb 3 v cc C0.2v, f = 0 1.0 v ai03859 data retention mode tr 1.95v tcdr v cc 1.65v v dr > 1.0v e or ub/lb e 3 v dr C 0.2v or ub = lb 3 v dr C 0.2v
15/17 M68AR256ML package mechanical figure 14. tfbga48 7x8mm - 6x8 ball array, 0.75 mm pitch, bottom view package outline note: drawing is not to scale. table 10. tfbga48 7x8mm - 6x8 ball array, 0.75 mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.260 0.0102 a2 0.900 0.0354 b 0.350 0.450 0.0138 0.0177 d 7.000 6.900 7.100 0.2756 0.2717 0.2795 d1 3.750 C C 0.1476 C C ddd 0.100 0.0039 e 8.000 7.900 8.100 0.3150 0.3110 0.3189 e1 5.250 C C 0.2067 C C e 0.750 C C 0.0295 C C fd 1.625 C C 0.0640 C C fe 1.375 C C 0.0541 C C sd 0.375 C C 0.0148 C C se 0.375 C C 0.0148 C C e1 e d1 d eb a2 a1 a bga-z22 ddd fd fe sd se e ball "a1"
M68AR256ML 16/17 part numbering table 11. ordering information scheme for a list of available options (e.g., speed, package) or for further information on any aspect of this device, please contact the st sales office nearest to you. revision history table 12. document revision history example: m68ar256 m l 55 zb 6 t device type m68 mode a = asynchronous operating voltage r = 1.65 to 1.95v array organization 256 = 4 mbit (256k x16) option 1 m = 1 chip enable; write and standby from ub and lb option 2 l = low leakage speed class 55 = 55 ns 70 = 70 ns package zb = tfbga48: 0.75 mm pitch operative temperature 1 = 0 to 70 c 6 = C40 to 85 c shipping t = tape & reel packing date version revision details july 2001 -01 first issue 23-oct-2001 -02 speed class changed from 80 to 70ns 20-may-2002 -03 document globally revised
17/17 M68AR256ML information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners. ? 2001 stmicroelectronics - all rights reserved stmicroelectronics group of companies austalia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com

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